A dynamic random access memory (DRAM) generally includes an array of bit cells, each cell capable of storing a bit of information. A typical cell configuration consists of a capacitor for storing a charge (i.e., the bit of information) and an access transistor that provides access to the capacitor during read and write operations. The access transistor is connected between a bitline and the capacitor, and is gated (turned on or off) by a wordline signal. During a read operation, the stored bit of information is read from the cell via the associated bitline. During a write operation, a bit of information is stored into the cell from the bitline via the transistor. The cells are dynamic in nature (due to leakage), and therefore must be periodically refreshed.
Embedded DRAM (eDRAM), where the capacitor is integrated on the same die as the processor (or other functional circuit having the DRAM), is implemented in a stacked configuration. Such stacked solutions are generally associated with a number of non-trivial problems.
As will be appreciated, the figures are not necessarily drawn to scale or intended to limit the claimed invention to the specific configurations shown. For instance, while some figures generally indicate straight lines, right angles, and smooth surfaces, an actual implementation of a memory device may have less than perfect straight lines, right angles, and some features may have surface topology or otherwise be non-smooth, given real world limitations of the processing equipment and techniques used. In short, the figures are provided merely to show example structures.